First update for 2022 school

README.md

@@ -2,4 +2,5 @@
 
 This repository contains documentation about the hardware that is being used during the summer school:
 
+- [Dardel Thin Compute Nodes](dardel/dardel-thin-cn.md)
 - [Tegner Thin Nodes](tegner/tegner-thin-node.md)

dardel/dardel-thin-cn.md

+# Dardel Thin Compute Nodes
+
+The Dardel Thin Compute Nodes comprise
+
+- 2x AMD EPYC 7742 CPUs with 256 GByte main memory attached
+- 1x Slingshot network card
+
+## CPU and host memory
+
+The AMD EPYC 7742 CPU belongs to the Rome generation and features features Zen 2 cores. The following picture provides an overview of the micro-architecture of the Zen 2 cores (source: [WikiChip](https://en.wikichip.org/wiki/amd/microarchitectures/zen_2)):
+
+<img src="zen_2_core_diagram.svg" alt="Haswell" width="500px"/>
+
+The following table documents key hardware parameters of the node:
+
+Parameter | Value 
+----------| -----
+Number of sockets | 2
+Number of cores per socket | 12
+SIMD ISA | AVX2
+FP64/cycle per core | 16
+FP32/cycle per core | 32
+Base frequency | 2.25 GHz
+Boost frequency | 3.4 GHz
+L1-I cache per core | 32 kiByte, 8-way set associative
+L1-D cache per core | 32 kiByte, 8-way set associative
+L2 cache per core | 512 kiByte, 8-way set associative
+L3 cache per socket | 256 MiByte
+Memory technology | DDR4
+Memory capacity per node | 256 GiByte
+Memory channels per socket | 8x64 bit
+Memory data rate | 3200 MT/s
+Memory bandwidth per socket | 204.8 GByte/s
+
+For more information see [AMD's product page](https://www.amd.com/en/products/cpu/amd-epyc-7742)
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tegner/tegner-thin-node.md

-# Tegner Thin Nodes
+# Tegner Thin Nodes with K80 GPU
 
-The Tegner Thin Nodes comprise
+The Tegner Thin Nodes with K80 GPU comprise
 
 - 2x Intel E5-2690v3 CPUs with 512 GByte main memory attached
-- 1x NVIDIA Quadro K420 GPUs
+- 1x NVIDIA Tesla K80 GPU
 - 1x Mellanox ConnectX-4 card (Infiniband EDR)
 
 ## CPU and host memory
 
-The Intel E5-2690v3 CPUs belongs to the Haswell generation. The following picture provides an overview of the micro-architecture of this kind of processors (source: [WikiChip](https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client))):
+The Intel E5-2690v3 CPU belongs to the Haswell generation. The following picture provides an overview of the micro-architecture of this kind of processors (source: [WikiChip](https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client))):
 
 <img src="1380px-haswell_block_diagram.svg.png" alt="Haswell" width="400px"/>
 
-The following table documents key hardware parameters of the CPU and the attached host memory:
+The following table documents key hardware parameters of the node:
 
 Parameter | Value 
 ----------| -----
@@ -37,25 +37,27 @@ For more information see [Intel's product page](https://ark.intel.com/content/ww
 
 ## GPU and device memory
 
-The NVIDIA Quadro K420 GPU belongs to the Kepler generation. It is optimised for graphics applications (unlike other GPUs of that generation that target, in particular, HPC applications and feature, e.g., much higher memory bandwidth and more memory capacity). The following table documents key hardware parameters of this GPU and the attached device memory:
+The NVIDIA Tesla K80 GPU belongs to the Kepler generation. It is optimised for graphics applications (unlike other GPUs of that generation that target, in particular, HPC applications and feature, e.g., much higher memory bandwidth and more memory capacity). The following table documents key hardware parameters of this GPU and the attached device memory:
 
 Parameter | Value
 ----------| -----
-GPU type | GK107
-Number of SMX | 1
-FP32/cycle per SMX | 384
-FP64/cycle per SMX | 16
-GPU clock | 876 MHz 
-32-bit registers per SMX | 65536
-L1 cache per SMX | 16 kiByte
-L2 cache per device | 256 kiByte
-Memory clock | 891 MHz
-Memory technology | DDR3
-Memory capacity per device | 1 GiByte
-Memory channels per device | 1x128 bit
-Memory data rate | 1800 MT/s
-Memory bandwidth per socket | 29 GByte/s
+GPU type | GK210
+Number of SMs | 2x13
+FP32/cycle per SM | 384
+FP64/cycle per SM | 128
+GPU base clock | 560 MHz 
+32-bit registers per SM | 65536
+L1 cache per SM | 16 kiByte
+L2 cache per device | 1536 kiByte
+Memory clock | 2500 MHz
+Memory technology | GDDR5
+Memory capacity per board | 2x12 GiByte
+Memory bus width per board | 2x384 bit
+Memory bandwidth per board | 2x240 GByte/s
 Bus interface | 16x PCIe GEN2
 Bus interface data rate | 10 GByte/s
 
-For more information see [NVIDIA's data sheet](https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/13720_DS_NV_Quadro_K420_Aug25_US_NV_HR.pdf) or the [GPU database at www.techpowerup.com](https://www.techpowerup.com/gpu-specs/quadro-k420.c2599).
+For more information see
\ No newline at end of file
+- [NVIDIA: Tesla K80 Data Sheet](https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/TeslaK80-datasheet.pdf)
+- [NVIDIA: Tesla K80 Board Specification](https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/Tesla-K80-BoardSpec-07317-001-v05.pdf)
+- [www.techpowerup.com: GPU database](https://www.techpowerup.com/gpu-specs/tesla-k80.c2616)
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